JTAG Defined | An Introduction to JTAG

by admin on August 11, 2008

JTAG What is it?

JTAG is an acronym that stands for “Joint Test Action Group”.

Group–in this case–was a group of vendors focused on problems found when testing electronic circuit boards. Key members included: TI, Intel and others.

JTAG is the informal name often used to describe the standard that resulted from the work of this group. Specifically, the standard is known as IEEE1149.1 Boundary-Scan.

The main problem that the JTAG group set out to solve was that traditional In-Circuit Test or ICT, was no longer as effective as it once was for board test. This change was due to the rise in use of surface mount devices such as Ball Grid Array (BGA) devices.

These new devices had their pins (called balls) on the bottom of the chip. When soldered down to a circuit board the pins could not be accessed as they were covered by the chip itself. As many of these modern ICs had many hundreds of pins it quickly became impractical to add test points for all the new pins.

BGA-IC

As you can see from the diagram above, BGA devices–once soldered in place–made it impossible to get at the pins of the device.

Standard JTAG Connector Signal Names

JTAG utilizes a standard set of signals to communicate with the IC or ICs under test. These signals taken together are know as the TAP or Test Access Port. The signal are:

  • TDI Test Data In (This is the data from the JTAG tool into the device under test or (DUT)
  • TDO Test Data Out (This is the data out of the last IC in the chain on the DUT back to the test tool)
  • TCLK Test Clock (This is the JTAG System CLOCK from the tool into the device)
  • TMS Test Mode Select (This signal from the tool to the device is used to minipulate the internal state machine that controls Boundary-Scan operation)
  • TRST Test Reset ( This is an optional signal, often used with JTAG emulation or when multiple chains must be tied together)

How JTAG/Boundary-Scan Solves the Pin Access Issue

The pins that comprise the TAP interface are used to control the access to a long chain of I/O cells at each pin of a device. By clocking data patterns in and reading values out, it is possible to set and determine the state of a pin. By extension, since other non-JTAG devices may be connected to these pins, those devices can often be tested as well.

JTAG Terminology

People use the term JTAG loosely to describe test and debug interfaces based on the specifications brought about by this group. You may hear the term JTAG Boundary-Scan (used for board test and IEEE1149.1) and JTAG ICE or emulator.

JTAG emulators leverage extended registers and boundary-scan instructions, put on-chip by the processor manufacturer. These extra features, allow the JTAG connector to be used to control a microprocessor (Run, stop, step and read/write memory and registers). This type of tool is used for hardware bring up and embedded firmware debug.

JTAG Boundary-Scan Test tools allow the hardware level debugging, programming and testing of circuit boards.

For additional sections from this series, please visit the JTAG section of this Blog.

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JTAG Pinout FPGA

by admin on July 20, 2009

JTAG  Field Programmable Gate Array (FPGA) Pin out – “Standard (CES)”

This standard configuration is typically used for FPGA (such as Xilinx) JTAG programming adapters. You can create a pinout to use our JTAG system using the description below.

FPGA JTAG Header Connector Pinout

FPGA JTAG Connector Pinout

Pin Number                Signal name                  Signal Description

1                                      TCK                                   Test Clock Signal

2                                    Ground                             Ground

3                                    TDI                                     Test Data In

4                                   Ground                              Ground

5                                   TDO                                     Test Data Out

6                                  VCC                                      VCC Supply

7                                  TMS                                     Test Mode Select

8                                   TRST                                   Test Reset Signal

For additional Pinout and connector information for other tools and devices, please visit our JTAG Connector Pinout Page.

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JTAG Pinouts and Connectors for PowerPC

by admin on June 8, 2009

This page contains details on PowerPC JTAG Connector Pinouts. These Pinouts can be used to interface a JTAG ICE or Boundary Scan test Device to your PowerPC board

PowerPC 52XX, 74XX, 7XX, 82XX, 83XX, 85XX JTAG
Pin Signal Name
1 1  TDO
JTAG Test Data Out
2 2 Not Used (QACK -7XX only)
3 3 TDI
JTAG Test Data In
4 4 TRST
JTAG Test Reset
5 5  Not used
6 6 Vcc Target
1.8 – 5.0V:
This is the target reference voltage.
7 7 TCL Clock
8 8 CHK_STP_IN
9 9 TMS
JTAG Test Mode Select
10 10 Not Used
11 11 /SRESET
12 12 Not Used
13 13 /HRESET
14 14 Not Used
15 15 CHK_STP_OUT
16 16 GROUND
System Ground
PowerPC 4XX JTAG
Pin Signal name
1 TDO
JTAG Test Data Out
2 2 Not Used
3 TDI
JTAG Test Data In
4 4 /TRST
JTAG Test Reset
5 5 Not used
6 6 Vcc Target
1.8 – 5.0V:
This is the target reference voltage.
7 7 TCK
JTAG Test Clock
8 8 Not Used
9 9 TMS
JTAG Test Mode Select
10 10 Not Used
11 11 /SYS_HALT
12 12 Not Used
13 13 Not Used
14 14 Not Used
15 15 Not Used
16 16 GROUND
System Ground

Please visit our JTAG pinout and Connector page for additional information.

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JTAG Pinout Xilinx Cable IV

by admin on June 8, 2009

The pin out below is for the 14-pin Xilinx Cable IV. Our XJLink can be used in place of this cable to program and configure Xilinx FPGAs and it can also be used to provide complete boundary scan testing for your board.

1 VGND   2 VREF
3 GND    4 TMS
5 GND    6 TCK
7 GND    8 TDO
9 GND    10 TDI
11 GND   12 NC
13 GND   14 NC
Please refer to our JTAG Connector Page for additional tool and device information.

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JTAG Connector Pinouts

by admin on June 8, 2009

This page is a resource for JTAG connectors. It contains information on JTAG connector: pin-outs, connector vendors, JTAG tool Pin outs, JTAG device Pinouts. This information can be used to help you create custom connectors to connect your JTAG hardware to our XJLink controller. Each week we will add new connector pin descriptions. Please let us know if you would like us to add a specific product or device.

If you are interested in learning about our JTAG Test and In-Circuit Programming Tools, please visit our JTAG Tools Page or Send us a message . If you would like to speak with an Engineer about our JTAG Products please call us on(800)-928-6038

JTAG Tool Connector Pin outs

Programming/Test Cables

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JTAG Pinout Altera ByteBlaster II

by admin on June 8, 2009

ByteBlaster Cable Pinout

ByteBlaster Cable Pinout

The Altera ByteBlaster II pin out is shown below. The JTAG signal are show along with there pin numbers. Our XJLink JTAG controller hardware fully supports this pin out as well as many other standard programming and confoiguration cabled. Since our  XJLink controller can replace the BYteBlaster II cable

For additional information on the cable, fully supports Altera CPLD configuration and configuration, it can replace the ByteBlaster II. In addition our Hardware supports programming for all common devices and boundary scan test.

Pin 1 TCK Target Clock
Pin 2 GND ground
Pin 3 TDO Target Data Out from the device
Pin 4 VCC Power
Pin 5 TMS JTAG Test Mode Select (Controls the JTAG State Machine)
Pin 6   No connection
Pin 7   No connection
Pin 8   No connection
Pin 9 TDI Target Data into the device
Pin 10 GND ground

For Pinout and connector information for other tools and devices, please visit our JTAG Connector Pinout Page.

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Boundary Scan

by admin on August 14, 2008

Boundary Scan

What is Boundary-Scan, What is it used for? Boundary Scan is used to test, program and debug printed circuit boards (PCBs).

Let’s begin with a bit of history on why Boundary Scan came about.

Why is Boundary Scan Needed

Back in the late 80’s and early 90’s, several developments in Circuit Board technology came together to make board test more difficult, namely:

  1. The move to surface mounted devices
  2. The use of Multilayer Circuit boards
  3. The lack of test points on circuit boards, due to these issues

As a result of these changes, traditional in-circuit test (ICT) tools, so-called bed of nails testers were no longer able to fully test Printed circuit boards (PCBs). To address this vexing problem, a consortium of companies–known as the Joint Test Access Group or JTAG was formed.

What Can You Do With Boundary Scan?

There are several levels of testing supported by Boundary Scan: Chip Level and Board Level.

in addition, Boundary-Scan tools can be leveraged at various phases of the development lifecycle, namely: The Design phase, The Prototype Debug Phase, The Production Phase and the Field Repair Phase.

The following sections will introduce these functional areas of test.

Chip Level Boundary Scan Testing

Boundary Scan allows you to do the following types of chip level testing:

  • Presence of the device – Is the device on the board; did it get soldered on.
  • Orientation of the device – Is it oriented correctly; is it rotated, shifted, the wrong package…
  • Is it bonded to the board – Is it soldered properly or are their issues with the solder joint, is the internal pin to amplifier interconnect damaged?
  • Read the devices ID register (get chip revision level information), Verify Basic operation

Board Level Testing Boundary Scan Testing

Testing at the board level adds inter-device and board-level testing such as:

  • Ability to verify the presence and integrity of the entire scan chain and each device on it.
  • Device interconnect tests
  • Open, Short and Stuck At (0,1) failures
  • Cluster (non-jtag) device testing such as: DDR2 RAM, Ethernet MAC/PHY, FLASH, CPLD, FPGA, etc..

The Value of Boundary Scan Throughout the Development Life Cycle

This section will detail the value of Boundary Scan at the various phases of product development.

PCB Design Phase: Design for Test (DFT) Factors

Test coverage and overall product quality are crucial to a products success. If a product needs to be recalled or repaired in the field (so-called “truck rolls), the effects can be devistating to the bottom line.

When designing printed circuit boards, one of the key things you can do to improve overall quality is to adhere to design for test (DFT) guidelines. Basically, DFT guidelines help you created systems with a high degree of test coverage so that you can catch as many defects as possible before you ship your product.

The key way to increase overall test coverage with boundary scan is the use of IEEE 1149.1 compliant devices. These devices should be placed strategically in your design to provide access to as many devices and nets as possible.

If you are working on products that require long, labor intensive operations to change or even systems that cannot be changed at all due to testing constraints like FDA, etc, you will also want to consider embedded hardware diagnostics to compliment your over all test picture.

Additional DFT information can be found in the post entitled: Design for Test.

PCB Prototype Debug and Bring Up Phase

When bringing up and debugging your new hardware, Boundary Scan comes to the rescue in several important ways:

Testing Partially Populated hardware

When you get your initial boards, not all devices may be fitted. That’s fine, with Boundary Scan, you only need good power, ground and at least one part on the JTAG Chain to begin testing. You should be able to ID the part on the chain and then test for opens and shorts for any board area that is touched by this device.

Initilizing and Programming Devices

You may also be able to do initial device programming. For example, if the device on the chain is a microprocessor or DSP, most likely you will have access to RAM and FLASH memory via the address, data and control bus. This can allow you to ID and Program and test these so-called (cluster, or non-jtag) devices. FPGAs, CPLDs (XILINX and ALTERA, for example) may also fall into this category.

Finding Assembly Defects

Prototypes are often rushed through assembly in order to make engineering deadlines. As a result, assembly and manufacturing problems will exist. Boundary Scan is prefect for testing for common problems like unfitted or ill fitted devices, solder issues (cold or hot Joints), as well as open, shorts, stuck at and device functional failures.

Improving Debug Productivity

As initial firmware or diagnostics are written for your new hardware, Boundary Scan can be used to rule out “bad hardware” by providing a “golden” test that validates that a board is good. With this type of testing, you will be able to focus your debug efforts on the new release of firmware, knowing full well that your hardware is good.

Production Test Phase

Manufacturing test is the clearly sweet spot for Boundary Scan. It was designed to compliment existing test methods and to over come the problems of evolving board technology.

Quality Control

Boundary Scan can be provided to external Contract Manufacturers on in-house manufacturing sites as a way to control and audit they types of testing that they do as well as a way to increase overall quality.

Part of Comprehensive Tests

Boundary Scan can be used as a part of a comprehensive test environment including ICT, Visual and XRAY inspection and thermal test.

Sub-Assembly Support

As part of the production process sub-assemblies from the CM can be tested in-house to avoid infant failures and the need for rebuilds in production.

Device Programming

As previously mentioned devices can be programmed via JTAG boundary Scan. CPLD and FPGA images can be loaded as well as boot loader code and diagnostics software. Boundary Scan also makes a perfect tool for production test repair stations that allow test engineers to troubleshoot complex and expensice boards in the “bone yard”.

Field Service and Repair

Modern Boundary Scan tools can be quite portable and low cost allowing them to be used by the field service staff for board level troubleshooting and repair and device configuration.

Boundary Scan: Where to Get the Specification

If you would like to get the “official” Boundary-Scan spec, please follow the link below:

The IEEE 1149.1 Boundary Scan Spec

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JTAG Boundary-Scan Vs. JTAG Emulation (ICE)

by admin on August 4, 2007

One question that I often hear is: “What’s difference between JTAG Boundary-Scan Test and JTAG Emulation or a JTAG ICE?”

First off, these two methods share common functions such as: hardware bring-up, device programming and even some basic hardware test functionality. The big difference is that test systems are designed to do extensive hardware testing of circuit boards and ICE tools are predominantly used to debug hardware and firmware.

While the implementation is often different, the result is the same. Let’s take a look at both methods:

JTAG Boundary Scan Test

JTAG tools are extremely powerful and are an excellent way to do device programming and board testing. In Boundary-Scan mode the JTAG chain is essentially a serial shift register that runs throughout a device.

Reading and External Device Pins

Each external pin can be set to a state or have it’s state read by manipulating the internal JTAG state machine. If you want to read a pin, figure out how many bits to stuff into the serial register, set up the state machine and clock them through. When the shifting is done, you will have the value that you need.

Writing to External Device Pins

Conversely, for setting pins, you would load the pattern up, set up the state machine and shift the bits out until they reached the pins in question.

Testing Multiple Devices on a JTAG Chain

To allow for board testing, boundary-scan enabled chips are daisy-chained together. The TMS and TRST lines are shared by every device, while the TDI and TDO lines form the daisy chain connections. The result is one long scan chain.

By reading pins and clocking out data and by writing pins via JTAG, any pin on any JTAG enabled device can be easily tested. Of course, this description is greatly simplified. In reality there are ways to put devices in so called “bypass” mode allowing them to be skipped over and ignored.

Devices can also be placed in transparent mode allowing signals to be passed through them. This Pass-through mode along with adherence to design for test (DFT) rules allows devices that are off the scan chain to be tested.

Fault Detection and API Access

Using this scheme, JTAG Boundary Scan Test tools can detect opens, shorts and “stuck at” faults on a system under test.

Using APIs and macro language interfaces, even complex device like Ethernet transceivers can be tested at an electrical and a basic functional level. Finally, programmable devices like: FLASH Memory, CPLDs, and FPGAs can be programmed in-circuit.

JTAG Emulation or JTAG ICE

A JTAG Emulator or ICE typically uses JTAG as well. (Some devices, like the Freescale Coldfire family use a BDM debug interface, while others like the Freescale MPC555 use the NEXUS interface.)

Assuming that JTAG is used–as it is on a popular device like the ARM9 core–the intent is more typically for hardware and software debug and FLASH Programming as opposed to Test.

When used as an ICE, JTAG controls and runs the microprocessor. In test mode, the processor is typically not running. An ICE also uses JTAG to communicate with the processors internal resisters allowing them to be set or read by the tool.

Special Processor Registers Support JTAG Debug

With an ICE, special registers controlled by JTAG in the processor are used to support debug functions like: Step, breakpoint, stop, run, memory and register read and write. IN order to do complex operations quickly, the JTAG channel is often used to set up the processor and it’s peripherals to work with RAM and FLASH in the system. Once the system is set up, programs can be spoon-fed to the processor’s RAM by the ICE. This is very powerful, since it all happens before the system is up and running user code.

Feel free to ask questions of leave comments

Thanks

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Design for Test (DFT)

by admin on July 12, 2007

When designing new hardware that employs Ball Grid Array (BGA) devices, it is critical to adhere to design for test (DFT) guidelines. Provided that you have JTAG enabled devices on your board, DFT guidelines allow you to design your board in such a way that the highest possible percentage of your hardware is tested. Many Boundary Scan Test tool vendors provide design for test guides for you to use.

These guides are based on the IEEE 1149.1 (JTAG) Boundary Scan standard as well as good hardware design practice.

DFT guidelines cover the following general areas:

Ensure proper power and ground connections

Verify compliance with the IEEE 1149.1 Spec

Ensure that the JTAG Chain is properly connected between devices

Verify that your Boundary Scan Definition File (BSDL) file is good for the device you want to test

Keep signal length to a minimum

Watch Clock Skew

Be sure to Buffer the JTAG Signals Properly

Make sure that Extra Pins are available near Non Boundary Scan Devices

Be Sure that Programmable devices like FLASH and EPLDs are near Boundary Scan enabled Devices

Our Partner XJTAG has created an very complete Design for Test Document which you can refer to as you design your new hardware.

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