What is JTAG

JTAG is an acronym that stands for “Joint Test Action Group”.

The group was a consortium of vendors focused on problems found when testing electronic circuit boards. Key members included: TI, Intel and others. JTAG is the informal name often used to describe the standard that resulted from the work of this group. Specifically, the standard is known as IEEE1149.1 Boundary-Scan.

JTAG Terminology

People use the term JTAG loosely to describe test and debug interfaces based on the specifications brought about by this group. You may hear the term JTAG Boundary-Scan (used for board test and IEEE1149.1) and JTAG ICE or emulator.

JTAG emulators leverage extended registers and boundary-scan instructions, put on-chip by the processor manufacturer. These extra features, allow the JTAG connector to be used to control a microprocessor (Run, stop, step and read/write memory and registers). This type of tool is used for hardware bring up and embedded firmware debug.

JTAG Boundary-Scan Test tools allow the hardware level debugging, programming and testing of circuit boards.

For additional sections from this series, please visit the JTAG section of this Blog.

Problems Caused By Surface Mount Devices

The main problem that the JTAG group set out to solve was that traditional In-Circuit Test or ICT, was no longer as effective as it once was for board test. This change was due to the rise in use of surface mount devices such as Ball Grid Array (BGA) devices. (The ever decreasing size of modern electronic circuits and the rise of multi-layer printed circuit boards were also key drivers for JTAG.)

These new devices had their pins (called balls) on the bottom of the chip. When soldered down to a circuit board the pins could not be accessed as they were covered by the chip itself. As many of these modern ICs had many hundreds of pins it quickly became impractical to add test points for all the new pins.

As you can see from the diagram to the left, BGA devices–once soldered in place–made it impossible to get at the pins of the device.

How JTAG/Boundary-Scan Solves the Pin Access Issue

The pins that comprise the TAP interface are used to control the access to a long chain of I/O cells at each pin of a device. By clocking data patterns in and reading values out, it is possible to set and determine the state of a pin. By extension, since other non-JTAG devices may be connected to these pins, those devices can often be tested as well.

Standard JTAG Connector Signal Names

JTAG utilizes a standard set of signals to communicate with the IC or ICs under test. These signals taken together are know as the TAP or Test Access Port. The signals are:

• TDI Test Data In (This is the data from the JTAG tool into the device under test or (DUT)
• TDO Test Data Out (This is the data out of the last IC in the chain on the DUT back to the test tool)
• TCLK Test Clock (This is the JTAG System CLOCK from the tool into the device)
• TMS Test Mode Select (This signal from the tool to the device is used to minipulate the internal state machine that controls Boundary-Scan operation)
• TRST Test Reset ( This is an optional signal, often used with JTAG emulation or when multiple chains must be tied together)