July
12

When designing new hardware that employs Ball Grid Array (BGA) devices, it is critical to adhere to design for test (DFT) guidelines. DFT guidelines allow you to design your board in such a way that the highest possible percentage of your hardware is tested. Many Boundary Scan Test tool vendors provide design for test guides for you to use.

These guides are based on the IEEE 1149.1 (JTAG) Boundary Scan standard as well as good hardware design practice.

DFT guidelines cover the following general areas:

Ensure proper power and ground connections

Verify compliance with the IEEE 1149.1 Spec

Ensure that the JTAG Chain is properly connected between devices

Verify that your Boundary Scan Definition File (BSDL) file is good for the device you want to test

Keep signal length to a minimum

Watch Clock Skew

Be sure to Buffer the JTAG Signals Properly

Make sure that Extra Pins are available near Non Boundary Scan Devices

Be Sure that Programmable devices like FLASH and EPLDs are near Boundary Scan enabled Devices

Our Partner XJTAG has created an very complete Design for Test Document which you can refer to as you design your new hardware.

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