This article reflects the questions that I hear most often from people who are new to Boundary Scan. It should give you a good practical overview of the technology.
WIN A FREE BOUNDARY SCAN BOOK (over $100.00 value!) – I plan to keep adding to this post over time so please submit any questions that you have in the comments section. As an incentive to post your questions, the best question each month wins a FREE copy of the Boundary Scan Handbook!
What is Boundary Scan used for?
Boundary Scan is used for a several things, most notably:
- Initial Board/Prototype bring up and debug
- Device programming
- Production/Manufacturing test
- Board repair in manufacturing (AKA clearing the bone-yard!)
- Field service and field debug
- Hacking and reverse engineering
Where does Boundary Scan fit into the product development life-cycle?
Boundary Scan is used in several phases of the product development life-cycle from development through manufacturing test and field repair. In the figure above note how Boundary Scan can be leveraged at each phase.
Who uses Boundary Scan?
Boundary Scan is used by:
Design Engineers – who are responsible for hardware design and bring up and who also want to create tests for use in manufacturing.
Test Engineers - responsible for creating tests for manufacturing and board repair.
Production Test Operators – who are responsible for running the tests in a production environment and often for board repair as well.
How does JTAG apply to Boundary Scan, I keep hearing them used interchangeably?
JTAG is an acronym for Joint Test Action Group, which was the group formed in the 1980s to create a technology that could improve test coverage as boards got smaller and more densely populated with new surface mount package types. Today you will often hear people call this test technology JTAG or JTAG Boundary Scan or just Boundary Scan.
How does Boundary Scan work?
There are many articles on this topic so I won’t go into great detail. (Here is a good article and video about Boundary Scan.) The key is that ICs have special logic added between their external pins and internal logic. These Boundary Scan cells allow each pin to be used as a test point in your circuit. Since the test points are built into the chip, there is no reason to add them to the circuit board itself.
What kind of test coverage should I expect from JTAG Boundary Scan?
Coverage will vary widely depending on a number of things, here is a partial list:
The number of devices on the board that support Boundary Scan
Which nets (connection points between devices) are reachable by devices that support Boundary Scan
The types of devices on the board. Standard IEEE 1149.1 is a digital test technology and as such it cannot by default handle analog devices. Other IEEE specs cover other issues like AC-coupled nets testing, here is a good overview video. You can also get creative and use I2C access (under Boundary Scan control) to access some analog devices.
You can improve coverage with careful planning. For best results you should always consider design for test issues early in the design as opposed to it being an afterthought.
How can I improve Boundary Scan test coverage?
As mentioned above, the more device that support Boundary Scan on your board the better. You should also make sure that is is possible to turn off (via Boundary Scan) the outputs of any devices that drive nets that you would like to test. You can also improve overall test coverage by using Boundary Scan with other technologies and discussed in the next section.
How can other tools compliment Boundary Scan?
Boundary Scan is part of a continuum of test; it is typically used with other technologies like:
- Optical Inspection
- XRAY
- Functional Test
- Boot Diagnostics
- In-Circuit Test (ICT)
- Flying Probe
How much does Boundary Scan cost?
Boundary Scan tools run the gamut in terms of pricing from a few hundred dollars all the way up to over 30,000 dollars. As you would expect you get what you pay for so be sure to try out any product before you buy.
Is there a standard connector for Boundary Scan?
Nope, the signals are defined: TDI, TDO, TCK, TMS and optionally TRST but the actual connector is left to to the designer. This does allow for maximum flexibility when trying to fit a test connector on a tiny board.
Here is a good post on some of the connectors used with JTAG Boundary Scan.
Thanks for reading and don’t forget to leave your questions in the comments section.

{ 1 comment… read it below or add one }
can we test the boundary scan chips through software?…..
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