JTAG IEEE Standards: IEEE 1149.1, IEEE 1149.6, IEEE 1149.7

 

JTAG Standards

Welcome to this introduction to three key JTAG Standards.
These standards are the most active and commonly used and of most practical value for anyone who wants to employ JTAG Boundary SCAN tools today.

At the end of this post we will provide links to additional detail on each of these specifications.

If you prefer video, please take a look at the one on the right.

If you have questions please leave a comment at the end of the article.

IEEE 1149.1 JTAG

IEEE 1149.1 standard describes  the core functionality for JTAG Boundary Scan as it applies to digital circuit testing.
IEEE 1149.1 uses a five-pin Test Access Port (TAP) with one optional pin called: TRST. Here is a list of the standard pins used for JTAG Boundary Scan.

(Please note that there is no standard connector defined as part of the spec.)

  • TDI – Test data in (into the IC, from the tool)
  • TDO – Test data out (out of the IC, to the tool)
  • TCK – JTAG clock
  • TMS – Test mode select, used to initialize and control the state machine
  • TRST – Target Reset (optional)

1149.1 uses “pins-out” or “virtual nails” testing and can test for:

  • Device placement
  • Device type
  • Opens, shorts and stuck-at faults

It can also:

  • Program and configure FPGAs
  • Configure and program CPLDs
  • Program FLASH devices (both NAND and NOR)

The standard supports functional test on
“cluster” or non-JTAG devices such as:

  • Static and Dynamic RAM (DDR, QDR and others)
  • FLASH (both NAND and NOR devices)
  • Buses like I2C and even PCI.

Finally in a mode called emulation mode or processor controlled test, it supports at-speed functional test by using JTAG to load code to a processor on the board processor and run it.


IEEE 1149.6 JTAG

Eleven forty-nine dot six adds support AC coupled nodes like LVDS.
It allows you to test by sending pulses back and forth between devices using cells that support LVDS signals.
In order to do this sort of testing you are required to have a cell with dot six support at each end of the bus.

IEEE 1149.7 JTAG

IEEE 1149.7 is a super-set of IEEE 1149.1 It provides increased capability and decreases the pin count on the TAP controller from five pins down to two. (1149.7 only requires the TMS and TCK signals)
This scheme reduces the number of pins needed on the IC for control and test.

For fast, direct access to devices 1149.7  supports a star configuration.

Getting More Information About the Specifications

For additional information on the IEEE specifications please visit:
www.standards.ieee.org.

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