JTAG Test

What is JTAG Testing

Testing with JTAG allows you to test printed circuit boards for manufacturing defects, functional failures and even program and configure devices like FPGAs, CPLDs and FLASH.

So Why Use Boundary Scan Testing?

The key advantage of JTAG test over other test methods is that it requires a minimum number of test points (connections to the hardware under test) to do it’s work. Using Just 4 signals (and 1 optional signal), JTAG can fully test a wide variety of electronic products.

As circuit boards get smaller and test points become harder and harder to add to your design, JTAG is emerging as the preferred method for circuit board test.

How is Testing with JTAG Implemented?

Chip manufacturers includes special cells on each of the ICs  pins to facilitate test. These pins act as test agents; supporting read/write  access to signals at the pin.

In test mode the  internal logic if the chip is also disconnected from the external pins.

The JTAG interface lets you shift bit patterns to each of the pins and to read back the values found on pins.

As show in the diagram above, by driving signals between connected devices, nets can be tested for opens, shorts and stuck-at failures.

What Types of Testing Can I Do With JTAG

JTAG/Boundary Scan can be used for finding manufacturing defects like solder joint failures, shorts, opens stuck at failures as well as functional testing and device programming. Let’s take a look at each of these in more detail:

Chip-Level Test Using JTAG

Engineers have found JTAG ideal for IC testing.

Designers need to fully exercise the test IP that they have embedded in their custom chip and, to test the chip itself–JTAG makes this easy. Most modern chips use JTAG as the primary interface to these internal islands of testability such as BIST, RAM Tests and of course, JTAG Boundary Scan.

To implement this type of testing, a low-level applications programmer’s interface (API) is used to access the JTAG at the state-machine level. Registers that control test IP are accessed via low level JTAG commands called SCAN IR (SCAN Instruction Register)  and SCAN DR (SCAN Data Register). Using these commands, the device can be fully tested.

Board-Level Testing with JTAG Boundary Scan

Testing circuit boards is one of the primary uses of JTAG.  To create tests for a board, you simply enter a net list from your schematic capture tool and the Boundary Scan Definition Language File (BSDL file) for each chip in your design that supports boundry scan.

Using this information, the tool is able to sort out which nets are connected to which and the best way to test them.

Next you answer some questions about the devices on your board to help the system to fully understand your design, devices like resisters, jumpers and other passive devices along with non-JTAG device are described using a GUI.

Once you have completed the configuration, the system will automatically generate a connection test that can detect opens, shorts and stuck at errors on the board.

Finally a coverage map is produced showing you which areas are covered and which need additional testing.

System-Level test Using JTAG

JTAG tools can be configured to support multiple boards that comprise a complete system. Daughter boards, loop-back connectors and dongles can all be included in the test description allowing you to test systems of any level of complexity.

JTAG can also be integrated with other tools such as flying probe testers and ICT equipment to provide comprehensive testing for your design.

Functional Testing

JTAG can be used to do basic functional testing of your hardware. Since JTAG is a serial interface, devices will not be tested at full speed but can be tested for general operation. For at speed tests see the later paragraph on PCT (processor controlled testing). Here are a couple of examples of JTAG test:

• RAM Test – Static and dynamic RAM including DDR and QDR can all be tested. The tests will not be at full speed, but in practice testing this way will find most manufacturing faults on the address data and control lines of the memory device.
• FLASH Testing – FLASH devices can be tested both destructively and non-destructively depending on your needs.
  

How a Connection Test Works

Our connection testing algorithm is significantly different from other implementations–we employ tri-state nets.  The advantage of having tri-state nets to diagnose short circuit faults is the ability to find shorts beyond series resistors.

Relying on driving a net high and reading back low, or visa-versa, because two nets are shorted together could miss a fault if it exists on the ‘far’ side of series resistors from the point of JTAG access.  The voltage drop across these resistors could allow each net to read back what was written thus missing the fault.

Processor-Controlled JTAG Test

Processor controlled test uses the same JTAG hardware interface and protocol as Boundary Scan testing, the difference is that the microprocessor on the board under test is used to implement  the tests.  Their are several advantages to this approach: flexibility and speed.

Speed

Since the JTAG tool is essentially spoon-feeding programs to the processor’s memory, any test that the processor can run can be used. Since the code runs at full speed on the processor, memory and device tests can also be run at full speed.

Flexibility

From a flexibility standpoint, processor controlled test compliments traditional boundary scan test by filling gaps not covered by boundary scan.

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