Category Archives for "Boundary Scan"

JTAG Pinout Xilinx Cable IV

The pin out below is for the 14-pin Xilinx Cable IV. Our XJLink can be used in place of this cable to program and configure Xilinx FPGAs and it can also be used to provide complete boundary scan testing for your board. 1 VGND   2 VREF 3 GND    4 TMS 5 GND    6 TCK 7 GND    8 […]

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JTAG Connector Pinout

This page is a resource for JTAG connectors.  These connectors are commonly used to interface Boundary SCAN tools or JTAG Emulators to a system under test. A common JTAG interface will have 4 or 5 standard signals (TDI, TDO, TMS, TCK, TRST) and some number of optional pins depending on the device. There is no […]

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Boundary Scan

Quick Navigation Why Boundary Scan?What Can You Do With it?Chip Level TestingBoard Level Testing Boundary Scan TestingValue Throughout the Board Test Life CyclePCB Design Phase: Design for Test (DFT) FactorsPCB Prototype Debug and Bring Up PhaseProduction Test PhaseField Service and Repair PhaseWhere to Get the Boundary Scan Spec Boundary Scan is a technology used to […]

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JTAG Boundary-Scan Vs. JTAG Emulation (ICE)

One question that I often hear is: “What’s difference between JTAG Boundary-Scan Test and JTAG Emulation or a JTAG ICE?” First off, these two methods share common functions such as: hardware bring-up, device programming and even some basic hardware test functionality. The big difference is that test systems are designed to do extensive hardware testing […]

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