Free DFT White Paper

 

We have created a Free Boundary SCAN DFT_Guidelines white paper which you can refer to as you design your new hardware.

Download your Free DFT_Guidelines White Paper.

When designing new hardware that employs JTAG/Boundary SCAN, and surface mount ICs, it is critical to adhere to design for test (DFT) guidelines.

Provided that you have JTAG enabled devices on your board, DFT guidelines allow you to design your board in such a way that the highest possible percentage of your hardware is tested.  This guide is based on the IEEE 1149.1 (JTAG) Boundary Scan standard as well as good hardware design practice.

DFT guidelines cover the following general areas:

  • Ensure proper power and ground connections
  • Verify compliance with the IEEE 1149.1 Spec – does the device support the mandatory instructions? Is there a BSDL file available that describes the how the devices supports the standard?
  • Ensure that the JTAG Chain is properly connected between devices – You can typically daisy chain TDI-TDO on each device and put TCK and TMS in common with all devices. You may also want to put in jumpers or some other means of remove one or more devices from a chain. Some devices do not play well with others.
  • Verify that your Boundary Scan Definition File (BSDL) file is good for the device you want to test = You may have the file, but in some cases it will have errors or perhaps be the wrong version for the device you are using.
  • Keep signal length to a minimum – always good advice for JTAG.
  • Watch Clock Skew – Some JTAG tools have hardware de-skew, but many do not.
  • Be sure to Buffer the JTAG Signals Properly
  • Make sure that Extra Pins are available near Non Boundary Scan Devices – these pins will give you test access to devices that you normally would not be able to access.
  • Be Sure that Programmable devices like FLASH and EPLDs are near Boundary Scan enabled Devices – most tools can program these devices in-circuit, but only if you provide proper access.

 

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