<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>Learn About JTAG</title>
	<atom:link href="http://www.etoolsmiths.com/feed/" rel="self" type="application/rss+xml" />
	<link>http://www.etoolsmiths.com</link>
	<description>JTAG and Boundary-Scan Tools</description>
	<lastBuildDate>Mon, 14 Sep 2009 03:07:55 +0000</lastBuildDate>
	<generator>http://wordpress.org/?v=abc</generator>
	<language>en</language>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
			<item>
		<title>JTAG Pinout FPGA</title>
		<link>http://www.etoolsmiths.com/blog/jtag-pinout-fpga/</link>
		<comments>http://www.etoolsmiths.com/blog/jtag-pinout-fpga/#comments</comments>
		<pubDate>Tue, 21 Jul 2009 06:26:26 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Boundary Scan]]></category>
		<category><![CDATA[JTAG]]></category>
		<category><![CDATA[JTAG Pinouts and Cables]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/?p=317</guid>
		<description><![CDATA[ JTAG  Field Programmable Gate Array (FPGA) Pin out &#8211; &#8220;Standard (CES)&#8221;
This standard configuration is typically used for FPGA (such as Xilinx) JTAG programming adapters. You can create a pinout to use our JTAG system using the description below.

Pin Number                 Signal name                   Signal Description
1                                      TCK                                   Test Clock Signal
2                                    Ground                             Ground
3                                    TDI                                     Test Data [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/jtag-pinout-fpga/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>JTAG Pinouts and Connectors for PowerPC</title>
		<link>http://www.etoolsmiths.com/blog/jtag-pinouts-and-connectors-for-powerpc/</link>
		<comments>http://www.etoolsmiths.com/blog/jtag-pinouts-and-connectors-for-powerpc/#comments</comments>
		<pubDate>Tue, 09 Jun 2009 04:00:01 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[JTAG Pinouts and Cables]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/?p=286</guid>
		<description><![CDATA[This page contains details on PowerPC JTAG Connector Pinouts. These Pinouts can be used to interface a JTAG ICE or Boundary Scan test Device to your PowerPC board




PowerPC                            [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/jtag-pinouts-and-connectors-for-powerpc/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>JTAG Pinout Xilinx Cable IV</title>
		<link>http://www.etoolsmiths.com/blog/jtag-pinout-xilinx-cable-iv/</link>
		<comments>http://www.etoolsmiths.com/blog/jtag-pinout-xilinx-cable-iv/#comments</comments>
		<pubDate>Tue, 09 Jun 2009 03:36:59 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Boundary Scan]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/?p=275</guid>
		<description><![CDATA[The pin out below is for the 14-pin Xilinx Cable IV. Our XJLink can be used in place of this cable to program and configure Xilinx FPGAs and it can also be used to provide complete boundary scan testing for your board.
1 VGND   2 VREF
3 GND    4 TMS
5 GND    6 TCK
7 GND    8 TDO
9 GND    10 TDI
11 [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/jtag-pinout-xilinx-cable-iv/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>JTAG Connector Pinouts</title>
		<link>http://www.etoolsmiths.com/blog/jtag-connector-pinouts/</link>
		<comments>http://www.etoolsmiths.com/blog/jtag-connector-pinouts/#comments</comments>
		<pubDate>Tue, 09 Jun 2009 03:06:42 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Boundary Scan]]></category>
		<category><![CDATA[JTAG]]></category>
		<category><![CDATA[JTAG Pinouts and Cables]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/blog/?p=10</guid>
		<description><![CDATA[This page is a resource for JTAG connectors. It contains information on JTAG connector:  pin-outs, connector vendors, JTAG tool Pin outs, JTAG device Pinouts. This information can be used to help you create custom connectors to connect your JTAG hardware to our XJLink controller. Each week we will add new connector pin descriptions. Please [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/jtag-connector-pinouts/feed/</wfw:commentRss>
		<slash:comments>4</slash:comments>
		</item>
		<item>
		<title>JTAG Pinout Altera ByteBlaster II</title>
		<link>http://www.etoolsmiths.com/blog/jtag-pinout-altera-byteblaster-ii/</link>
		<comments>http://www.etoolsmiths.com/blog/jtag-pinout-altera-byteblaster-ii/#comments</comments>
		<pubDate>Tue, 09 Jun 2009 01:27:39 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[JTAG Pinouts and Cables]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/?p=263</guid>
		<description><![CDATA[The Altera ByteBlaster II pin out is shown below. The JTAG signal are show along with there pin numbers. Our XJLink JTAG controller hardware fully supports this pin out as well as many other standard programming and confoiguration cabled. Since our  XJLink controller can replace the BYteBlaster II cable
For additional information on the cable, fully [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/jtag-pinout-altera-byteblaster-ii/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Boundary Scan</title>
		<link>http://www.etoolsmiths.com/blog/boundary-scan/</link>
		<comments>http://www.etoolsmiths.com/blog/boundary-scan/#comments</comments>
		<pubDate>Thu, 14 Aug 2008 18:35:27 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Boundary Scan]]></category>
		<category><![CDATA[JTAG]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/blog/?p=13</guid>
		<description><![CDATA[Boundary Scan
What is Boundary-Scan, What is it used for? Boundary Scan is used to test, program and debug printed circuit boards (PCBs).
Let&#8217;s begin with a bit of history on why Boundary Scan came about.
Why is Boundary Scan Needed
Back in the late 80&#8217;s and early 90&#8217;s, several developments in Circuit Board technology came together to make [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/boundary-scan/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>JTAG Defined &#124; An Introduction to JTAG</title>
		<link>http://www.etoolsmiths.com/blog/jtag-defined/</link>
		<comments>http://www.etoolsmiths.com/blog/jtag-defined/#comments</comments>
		<pubDate>Mon, 11 Aug 2008 14:05:58 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[JTAG]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/blog/?p=11</guid>
		<description><![CDATA[JTAG What is it?
JTAG is an acronym that stands for &#8220;Joint Test Action Group&#8221;.
Group&#8211;in this case&#8211;was a group of vendors focused on problems found when testing electronic circuit boards. Key members included: TI, Intel and others.
JTAG is the informal name often used to describe the standard that resulted from the work of this group. Specifically, [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/jtag-defined/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>JTAG Boundary-Scan Vs. JTAG Emulation (ICE)</title>
		<link>http://www.etoolsmiths.com/blog/jtag-boundary-scan-vs-jtag-emulation-ice/</link>
		<comments>http://www.etoolsmiths.com/blog/jtag-boundary-scan-vs-jtag-emulation-ice/#comments</comments>
		<pubDate>Sat, 04 Aug 2007 20:36:33 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Boundary Scan]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/blog/jtag-boundary-scan-vs-jtag-emulation-ice/</guid>
		<description><![CDATA[One question that I often hear is: “What’s difference between JTAG Boundary-Scan Test and JTAG Emulation or a JTAG ICE?”
First off, these two methods share common functions such as: hardware bring-up, device programming and even some basic hardware test functionality. The big difference is that test systems are designed to do extensive hardware testing of [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/jtag-boundary-scan-vs-jtag-emulation-ice/feed/</wfw:commentRss>
		<slash:comments>4</slash:comments>
		</item>
		<item>
		<title>Design for Test (DFT)</title>
		<link>http://www.etoolsmiths.com/blog/design-for-test-dft/</link>
		<comments>http://www.etoolsmiths.com/blog/design-for-test-dft/#comments</comments>
		<pubDate>Thu, 12 Jul 2007 09:47:21 +0000</pubDate>
		<dc:creator>admin</dc:creator>
				<category><![CDATA[Circuit Board Test]]></category>

		<guid isPermaLink="false">http://www.etoolsmiths.com/blog/design-for-test-dft/</guid>
		<description><![CDATA[When designing new hardware that employs Ball Grid Array (BGA) devices, it is  critical to adhere to design for test (DFT) guidelines. Provided that you have JTAG enabled devices on your board, DFT guidelines allow you  to design your board in such a way that the highest possible percentage of your  hardware [...]]]></description>
		<wfw:commentRss>http://www.etoolsmiths.com/blog/design-for-test-dft/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
	</channel>
</rss>
