# Guardian Setup for 405ep bubinga NO SDRAM Init
#
# Target Specific
#
#	play ppc_405ep_bubinga.def
#
# 
#guard_on
#
opt tar       405ep
opt volt      3.3
opt pins      form3
opt tclk      norm
opt tdo       norm
opt tdi       norm
opt autoexc   off
opt pipe      off
opt holddur   20000
opt runn      0
#
# Auto Board Init 
#
opt brdinit   off
opt brdopt    0x41

#
# Settings for Linux Debug
#
#opt mmu       off                 
opt mmu       tlb                 # to support linux debug
opt step thruexc|noextint
#opt ftimrs on                    # Freeze Timers when stopped
opt ftimrs off                    # off so PIBs will boot
#
# General Options
#
def - *
opt vec       high
opt memread   single
opt memwrite  burst
#opt memwrite  single
opt endian    big
opt step thruexc|noextint
#opt step      normal
opt trbrk     off
opt excmask   0xfffff
opt vchk      off
opt break     soft
opt trorg     inst
opt echo      on
opt brkerr    on
opt nlines    0x0
opt nlocs     0x40
opt ascii     on
opt ucase     off
opt iradix    16
opt poly      0xedb88320
#opt bloc      8bit
opt bloc      pci

#
# flash related settings
#
# if you plan to use workspace for faslh programming, you can use
#  a large TFTP buffer and a shorter timeout value
opt tsrvto    20
opt tbufsiz   16    # tftp rx buffer size -- workspace is fast, so bump to 16k  

# if worksace is not available or not working, use
#  a small TFTP buffer and a longer timeout value
#opt tsrvto   30
#opt tbufsiz   4    # tftp rx buffer size -- reduce to 4k if opt flwork off

#
#
# Reset the Target
# 
opt hreset    on   
opt reset     sys
opt clk 1
reset
wait 200

wr :spr 0x3ba 0x0                # dcwr
wr :spr 0x3fa 0x0                # dccr
wr :spr 0x3fb 0x0                # iccr
wr :spr 0x3d6 0x0                # evpr


# chip selects
#

wr.4 :dcr 0x12 0x0                 #  
wr.4 :dcr 0x13 0xfff18000          # ebc0_b0cr, Flash+SRAM 1M, 8-bit at 0xfff00000 
wr.4 :dcr 0x12 0x1                 #  
wr.4 :dcr 0x13 0xf0018000          # ebc0_b1cr
wr.4 :dcr 0x12 0x4                 #  
wr.4 :dcr 0x13 0xf0318000          # ebc0_b4cr
wr.4 :dcr 0x12 0x10                #  
wr.4 :dcr 0x13 0x4006000           # ebc0_b0ap
wr.4 :dcr 0x12 0x11                #  
wr.4 :dcr 0x13 0x4041000           # ebc0_b1ap
wr.4 :dcr 0x12 0x14                #  
wr.4 :dcr 0x13 0x1815000           # ebc0_b4ap
wr.4 :dcr 0x12 0x23                #  
wr.4 :dcr 0x13 0xb8400000          # ebc0_cfg


wr.4 :dcr 0xf0 0x11003             # cpc0_pllmr0
wr.4 :dcr 0xf4 0x8085523e          # cpc0_pllmr1

opt mmu tlb

wr msr 0x00  # if you enable cache, the step from reset will not work

# TLB for cache enable during demo code
wtlb itlb  0x00 0x00 0x000002c0 0x00000308  # enable write-thru cache for RAM at 0x0


## Setup SDRAM Controller (DDR SDRAM)
# SDRAM is used as workspace RAM for FLASH programming
#
#wr :dcr 0x10 0x20
#wr :dcr 0x11 0x00800000		       # SDRAM0_CFG - Disable SDRAM Controller
#wr.4 :dcr 0x10 0x40                #  
#wr.4 :dcr 0x11 0x82001             # sdram0_b0cr
#wr.4 :dcr 0x10 0x44                #  
#wr.4 :dcr 0x11 0x4082001           # sdram0_b1cr
#wr.4 :dcr 0x10 0x48                #  
#wr.4 :dcr 0x11 0x4082001           # sdram0_b2cr
#wr.4 :dcr 0x10 0x30                #  
#wr.4 :dcr 0x11 0x8b80000           # sdram0_rtr
#wr.4 :dcr 0x10 0x80                #  
#wr.4 :dcr 0x11 0x894016            # sdram0_tr
#wr.4 :dcr 0x10 0x20                #  
#wr.4 :dcr 0x11 0x80800000          # sdram0_cfg  - Enable SDRAM Controller


# speed things now that the CPU is set up
opt clk 16


#
# Flash Setup
#
#opt flbase    0xfff00000		# base for both amd29f040 devices
#opt fltype    amd29f
#opt flwidth   8
#opt flssize   0x10000
#opt flnsec    64
#opt flwork    on
#opt wsaddr    0x10000
#opt wssize    0x4000
#opt fltout    45


#guard_off