# Guardian Setup for Walnut Board 405gp
# $Id: $
#
# play ppc_405gp_walnut.def
#
#guardon
#
# Target Specific
#
opt tar       405gp
opt reset     sys
opt clk       16
opt volt      3.3
opt pins      form3
opt tclk      norm
opt tdo       norm
opt tdi       norm
opt autoexc   off
opt pipe      off
opt brdinit   off
opt runn      0x0
opt holddur   20000

#
# General Options
#
def - *
opt vec       low
opt memread   single
opt memwrite  single
opt endian    big
opt step      normal
opt trbrk     off
opt excmask   0xfffff
opt vchk      off
opt break     soft
opt trorg     inst
opt echo      on
opt bloc      pci
opt ubloc     0
opt brkerr    on
opt nlines    0x0
opt nlocs     0x40
opt ascii     on
opt ucase     off
opt iradix    16
opt poly      0xedb88320
opt tsrvto    20
opt tbufsiz   16
#
# Reset the Target
#
opt runn      0x100
reset
opt runn      0x0
#

wr :spr 0x3ba 0x0                # dcwr
wr :spr 0x3fa 0x0                # dccr
wr :spr 0x3fb 0x0                # iccr
wr :spr 0x3d6 0x0                # evpr


# Setup the 8 bit AMD Flash
#
wr :dcr 0x12 0x10
wr :dcr 0x13 0x9B015480		# EBCO_B0AP
wr :dcr 0x12 0x00
wr :dcr 0x13 0xFFF18000		# EBCO_B0CR
wr :dcr 0x12 0x11
wr :dcr 0x13 0x02815480		# EBCO_B1AP

wr :dcr 0x12 0x01	#Select PB1CR
wr :dcr 0x13 0xF0018000	#PB1CR: 1MB at 0xF0000000, r/w, 8bit
wr :dcr 0x12 0x12	#Select PB2AP
wr :dcr 0x13 0x04815A80	#PB2AP: Keyboard and Mouse
wr :dcr 0x12 0x02	#Select PB2CR
wr :dcr 0x13 0xF0118000	#PB2CR: 1MB at 0xF0100000, r/w, 8bit
wr :dcr 0x12 0x13	#Select PB3AP
wr :dcr 0x13 0x01815280	#PB3AP: IRDA
wr :dcr 0x12 0x03	#Select PB3CR
wr :dcr 0x13 0xF0218000	#PB3CR: 1MB at 0xF0200000, r/w, 8bit
wr :dcr 0x12 0x17	#Select PB7AP
wr :dcr 0x13 0x01815280	#PB7AP: FPGA
wr :dcr 0x12 0x07	#Select PB7CR
wr :dcr 0x13 0xF0318000	#PB7CR: 1MB at 0xF0300000, r/w, 8bit


#
# Write the SDRAM Controller Registers
#
#wr :dcr 0x10 0x20
#wr :dcr 0x11 0x0086400D		# SDRAM0_CFG - Disable SDRAM Controller
#wr :dcr 0x10 0x40
#wr :dcr 0x11 0x00046001		# SDRAM0_B0CR
#wr :dcr 0x10 0x48
#wr :dcr 0x11 0x01046001		# SDRAM_B2CR
#wr :dcr 0x10 0x30
#wr :dcr 0x11 0x05F00000		# SDRAM0_RTR
#wr :dcr 0x10 0x20
#wr :dcr 0x11 0x80800000		# SDRAM0_CFG - Enable SDRAM Controller



opt mmu tlb

wr msr 0x00  # if you enable cache, the step from reset will not work

# TLB for cache enable during demo code
# Entry		EPN		RPN			RPEND		SIZE	V		W			I				M			G				E		ZSEL		WR			EX			U0		PID
# 0		0x00000000	0x00000000	0x00FFFFFF	16M		Valid	Wr-through	Cache inhibit	0(bin)		Guard disabled	Big		0xE			Enabled		Enabled		Off		0x00000000
#
#wtlb itlb 0x0  0x00 0x00000000 0x00000000 
#wtlb itlb 0x1  0x00 0x00000000 0x00000000 
#wtlb itlb 0x2  0x00 0x00000000 0x00000000 
#wtlb itlb 0x3  0x00 0x00000000 0x00000000 
#wtlb itlb 0x4  0x00 0x00000000 0x00000000 
#wtlb itlb 0x5  0x00 0x00000000 0x00000000 
#wtlb itlb 0x6  0x00 0x00000000 0x00000000 
#wtlb itlb 0x7  0x00 0x00000000 0x00000000 
#wtlb itlb 0x8  0x00 0x00000000 0x00000000 
#wtlb itlb 0x9  0x00 0x00000000 0x00000000 
#wtlb itlb 0x10  0x00 0x00000000 0x00000000 
#wtlb itlb 0x11  0x00 0x00000000 0x00000000 
#wtlb itlb 0x12  0x00 0x00000000 0x00000000 
#wtlb itlb 0x13  0x00 0x00000000 0x00000000 
#wtlb itlb 0x14  0x00 0x00000000 0x00000000 
#wtlb itlb 0x15  0x00 0x00000000 0x00000000 
#wtlb itlb 0x16  0x00 0x00000000 0x00000000 
#wtlb itlb 0x17  0x00 0x00000000 0x00000000 
#wtlb itlb 0x18  0x00 0x00000000 0x00000000 
#wtlb itlb 0x19  0x00 0x00000000 0x00000000 
#
#wtlb itlb  0x00 0x00 0x000002c0 0x00000300  # wr-back 
wtlb itlb  0x00 0x00 0x000002c0 0x00000308  # enable write-thru cache for RAM at 0x0
#wtlb itlb  0x01 0x00 0xd00000c0 0xd0000308 

#wr msr 0x30  # if you enable cache, the step from reset will not work
#wr.4 :spr 0x3fa 0xff000000	# ICCR
#wr.4 :spr 0x3fb 0xff000000	# DCCR



# For Linux Debug
#
opt step noextint|thruexc        # No external Interupts while stepping
opt ftimrs on                    # Freeze Timers when stopped
#wtlb ivt 0x1fe 0 0x10000000 9 0   # Vmap Entry for Kernel Space Applications
#wtlb ivt 0x1ff 0 0xc0000000 9 0   # Vmap Entry for Kernel Space 
#


#opt clk       16

#
# Group: OCM0
#  Uncomment these "wr.4" lines to enable internal RAM at 0xD0000000
#  This space can be used as workspace for fast flash programming
#
#wr.4 :dcr 0x1a 0xd0000000          # ocm0_dsarc : on-chip 4K RAM to 0xD0000000(data)
#wr.4 :dcr 0x1b 0xc0000000          # ocm0_dscntl: on-chip 4K RAM, enabled, 2 clock cycles(data)
#wr.4 :dcr 0x18 0xd0000000          # ocm0_isarc : on-chip 4K RAM to 0xD0000000(inst)
#wr.4 :dcr 0x19 0xc0000000          # ocm0_iscntl: on-chip 4K RAM, enabled, 2 clock cycles(inst)

#  Uncomment these options for setting up for flash programming
#
# Flash Setup
#
#opt fltype    amd29f
#opt flwidth   8
#opt flbase    0xfff80000
#opt flssize   0x10000
#opt flnsec    8
#opt flwork    on
#opt wsaddr    0xD0000000
#opt wssize    0x1000
#opt fltout    20
#

#guardoff