# Guardian Setup for 440GP Ebony NO SDRAM Init # # play ppc_440gp_ebony.def # #guardon # # Target Specific # #def - * #def mmucr spr 0 0x3b2 0 4 opt tar 440gp #opt tar auto #opt volt 3.3 opt volt auto opt pins form3 opt tclk norm opt tdo norm opt tdi norm opt autoexc on opt pipe off opt holddur 40000 # # Auto Board Init # opt brdinit off #opt brdinit on opt brdopt 0x42 # # General Options # opt vec low opt memread single opt memwrite single opt endian big opt step normal opt trbrk off opt excmask 0xfffff opt vchk off opt break soft opt trorg inst #opt echo off opt brkerr on opt nlines 0x0 opt nlocs 0x40 opt ascii on opt ucase off opt iradix 16 opt poly 0xedb88320 opt dwe off opt bloc pci opt ubloc 0 # # flash related settings # # if you plan to use workspace for faslh programming, you can use # a large TFTP buffer and a shorter timeout value opt tsrvto 20 opt tbufsiz 16 # tftp rx buffer size -- workspace is fast, so bump to 16k # if worksace is not available or not working, use # a small TFTP buffer and a longer timeout value #opt tsrvto 30 #opt tbufsiz 4 # tftp rx buffer size -- reduce to 4k if opt flwork off # # Settings for Linux Debug # opt trorg inst opt mmu tlb #opt mmu off opt linver 0x0 opt k_spte 0x0 opt k_upte 0x0 opt step noextint|thruexc # No external Interrupts while stepping opt ftimrs off # Freeze Timers when stopped? # # Reset the Target # opt hreset on # opt reset sys #opt runn 0x400 # larger RUNN value may be needed of flash is blank opt clk 1 # try slowing clock if you have reset problems reset opt runn 0x0 # runn back to 0, otherwise memory operations will be slow # make sure DBCRs are clear #wr.4 :spr 0x134 0 #wr.4 :spr 0x135 0 #wr.4 :spr 0x136 0 # set IVPR high to make sure it doesn't overlap demo code space #wr.4 :spr 0x3f 0xfffd0000 # # Setup some TLBs # # Entry EPN ERPN RPN RPN_END SIZE V TS TPAR PAR1 PAR2 U0 U1 U2 U3 W I M G E UX UW UR SX SW SR PID # 0 0xF0000000 0x01 0xF0000000 0xFFFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 # FLASH at 0xF0000000 wr.4 :spr 0x3b2 0 # make sure the MMUCR is clear for the PID value wtlb itlb 0x00 0x00 0xf0000290 0xf0000001 0x0000043f # SDRAM at 0x00000000 # 1 0x00000000 0x00 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-through Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wr.4 :spr 0x3b2 0 # make sure the MMUCR is clear for the PID value wtlb itlb 0x01 0x00 0x00000290 0x00000000 0x0000083f # Internal registers at 0x1_40000000 # 2 0xE0000000 0x01 0x40000000 0x4FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wr.4 :spr 0x3b2 0 # make sure the MMUCR is clear for the PID value wtlb itlb 0x02 0x00 0xe0000290 0x40000001 0x0000043f # Internal registers at 0x2_00000000 ## 3 0xD0000000 0x02 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wr.4 :spr 0x3b2 0 # make sure the MMUCR is clear for the PID value wtlb itlb 0x03 0x00 0xd0000290 0x00000002 0x0000043f # 4 0xC0000000 0x00 0xC0000000 0x80000FFF 4K Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wr.4 :spr 0x3b2 0 # make sure the MMUCR is clear for the PID value wtlb itlb 0x04 0x00 0xc0000220 0xC0000000 0x0000043f ## 5 0xC0001000 0x00 0xC0001000 0x80001FFF 4K Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 #wr.4 :spr 0x3b2 0 # make sure the MMUCR is clear for the PID value #wtlb itlb 0x05 0x00 0xc0001210 0x80001000 0x0000043f ## 6 0x10000000 0x00 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 #wtlb itlb 0x06 0x00 0x10000290 0x00000000 0x0000043f #wr.4 :spr 0x3b2 0 # make sure the MMUCR is clear for the PID value # 7 0x80000000 0x03 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x07 0x00 0x80000290 0x00000003 0x0000043f # # Flash Chip Selects # wr.4 :dcr 0x12 0x23 wr.4 :dcr 0x13 0x17000000 # EBC0_CFG # 1 socketed Flash part at 0xFFF80000, but we'll use a larger area for a chip select #wr.4 :dcr 0x12 0x00000000 # Select EBC0_B0CR #wr.4 :dcr 0x13 0xFFF18000 # 1MB at 0xFFE00000, r/w, 8bit #wr.4 :dcr 0x12 0x00000010 # EBC0_B0AP #wr.4 :dcr 0x13 0x9B015480 # works wr.4 :dcr 0x12 0x00000000 # Select EBC0_B0CR wr.4 :dcr 0x13 0xFFE38000 # 2MB at 0xFFE00000, r/w, 8bit wr.4 :dcr 0x12 0x00000010 # EBC0_B0AP wr.4 :dcr 0x13 0x9B015480 # works #wr.4 :dcr 0x12 0x00000000 # Select EBC0_B0CR #wr.4 :dcr 0x13 0xFFE38000 # 2MB at 0xFFE00000, r/w, 8bit #wr.4 :dcr 0x12 0x00000010 # EBC0_B0AP #wr.4 :dcr 0x13 0x04055200 # Alternate 4M non-socketed Flash wr.4 :dcr 0x12 0x00000002 # Select EBC0_B2CR wr.4 :dcr 0x13 0xFF858000 # 4MB at 0xFF800000, r/w, 8bit wr.4 :dcr 0x12 0x00000012 # EBC0_B2AP wr.4 :dcr 0x13 0x04055200 ## set up internal SRAM at 0xc0000000 for workspace wr.4 :dcr 0x20 0xc0000380 # SRAM0_SB0CR, 8K RW Bank 0 at 0xc0000000 # # Flash Setup # This is setup by agile-db # #opt flbase 0xfff80000 #opt fltype amd29f #opt flwidth 8 #opt flssize 0x10000 #opt flnsec 8 #opt fltout 20 #opt flwork on #opt wsaddr 0xC0000000 #opt wssize 0x2000 opt clk 16 # increase clock after a reset #guardoff