# Guardian SE command file to set up AMCC 440GR Yellowstone target
#
# play ppc_440gr_yellowstone.def
#
#guardon
#
ver -v

opt tar 440gr
opt vec high
opt holddur 20000
opt pipe off
opt autoexc off
opt brdinit off
#opt step      normal
opt step thruexc|noextint
opt trbrk off
opt excmask 0xfffff
opt vchk off
opt break soft
opt trorg data
opt runn 0x0
#opt dwe off
opt brdopt 0x0      
opt ftimrs off

#opt mmu off			# for flat translation
opt mmu tlb		# this will support linux debug
opt memread single
opt memwrite single
opt endian auto
opt bloc 16bit		# 16-bit boot location
opt ubloc 0xfffff000
#opt k_spte 0x0
#opt k_upte 0x0
#opt linver 0x0

opt clk 16
opt volt auto
opt pins form3
opt tclk norm
opt tdo norm
opt tdi norm
opt brkerr on
opt nlocs 0x40    # decimal = 64
opt ascii on
opt ucase off
opt poly 0xEDB88320
#opt rplay 
#opt bplay 


# flash related settings
opt wsaddr 0x10000
opt wssize 0x2000

opt flwork on	   # workspace on
opt tbufsiz 16   # tftp rx buffer size -- workspace is fast, so bump to 16k
#opt flwork off    # workspace off
#opt tbufsiz 2   # tftp rx buffer size -- reduce to 2k if opt flwork off

opt fltout 0x14    # flash operation timeout
opt flswap off
opt tsrvto 0x14    # tftp server timeout

# set this to the base address of your flash
opt flbase 0xfe000000
opt fltype amd29_d16  # flash algorithm
opt flssize 0x10000	  # sector size 
opt flwidth 16


#
#
# Reset the Target
# 
opt hreset    on   
opt reset     sys
opt clk 1
reset
wait 500


opt clk 16		# speed up for operations


#
# Soft-Reset the chip
#
#set SDR0_SRST.DMC = 0x1
wr.4 :dcr 0xe 0x00000200  # Select EBC0_B0AP Soft Reset Register
wr.4 :dcr 0xf 0x00200000  # DDR SDRAM memory controller
wait 100
#set SDR0_SRST.DMC = 0x0
wr.4 :dcr 0xe 0x00000200  # Select EBC0_B0AP Soft Reset Register
wr.4 :dcr 0xf 0x00000000  # DDR SDRAM memory controller

#wtlb itlb  0x0 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x1 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x2 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x3 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x4 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x5 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x6 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x7 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x8 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0x9 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0xa 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0xb 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0xc 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0xd 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0xe 0x0 0x00000000 0x00000000 0x0 
#wtlb itlb  0xf 0x0 0x00000000 0x00000000 0x0 

#setup TLBs
#wtlb itlb  0x0 0x0 0xfffff210 0xfffff000 0x43f 
#wtlb itlb  0x1 0x0 0x00000290 0x00000000 0xc3f  # cache off

wtlb itlb  0x0 0x0 0xf0000290 0xf0000000 0x43f 
wtlb itlb  0xf 0x0 0x00000290 0x00000000 0xc3f  # cache off
#wtlb itlb  0x0 0x0 0x00000290 0x00000000 0x83f  # cache on
wtlb itlb  0x1 0x0 0x10000290 0x10000000 0x43f 
wtlb itlb  0x2 0x0 0x20000290 0x20000000 0x43f 
wtlb itlb  0x3 0x0 0x30000290 0x30000000 0x43f 
wtlb itlb  0x4 0x0 0x40000290 0x40000000 0x53f 
wtlb itlb  0x5 0x0 0x50000290 0x50000000 0x43f 
wtlb itlb  0x6 0x0 0x60000290 0x60000000 0x43f 
wtlb itlb  0x7 0x0 0x70000290 0x70000000 0x43f 
wtlb itlb  0x8 0x0 0x80000290 0x80000000 0x83f 
wtlb itlb  0x9 0x0 0x90000290 0x90000000 0x43f 
wtlb itlb  0xa 0x0 0xa0000290 0xa0000000 0x43f 
wtlb itlb  0xb 0x0 0xb0000290 0xb0000000 0x43f 
wtlb itlb  0xc 0x0 0xc0000290 0xc0000000 0x43f 
wtlb itlb  0xd 0x0 0xd0000290 0xd0000000 0x43f 
wtlb itlb  0xe 0x0 0xe0000290 0xe0000000 0x43f 


# set IVPR high
#wr.4 :spr 0x3f 0xfffd0000

# 
#;;;;;;;;;;;;;;;;;;;;;;;;;;;FLASH CS0 32M x 16
wr.4 :dcr 0x12 0x00000010 # Select EBC0_B0AP
wr.4 :dcr 0x13 0x03017300 # B0AP: Flash
wr.4 :dcr 0x12 0x00000000 # Select EBC0_B0CR
wr.4 :dcr 0x13 0xfe0ba000 # B0CR: 32Meg, 16Bit at 0xFE000000

#;;;;;;;;;;;;;;;;;;;;;;;;;;;BCSR NVRAM CS2
#wr.4 :dcr 0x12 0x00000012 # Select EBC0_B2AP
#wr.4 :dcr 0x13 0x04814500 # EBC0_B2AP: BCSR
#wr.4 :dcr 0x12 0x00000002 # Select EBC0_B2CR
#wr.4 :dcr 0x13 0x80018000 # EBC0_B2CR: 1Meg, 16Bit at 0x80000000

#wm.4 0xef600b08 0x40010000 # Enable CS2, PerAddr07 pin GPIO0_OSRL
#wm.4 0xef600b10 0x40010000 # Enable CS2, PerAddr07 pin GPIO0_TSRL
#wm.4 0xef600b30 0x40000000 # Enable PerAddr07 pin


wr.4 :dcr 0x12 0x23                #  
wr.4 :dcr 0x13 0xb8400000          # ebc0_cfg

# GPIO setup for address lines for flash sizes larger than 16Meg
wm.4 0xef600b00  0x0               # gpio0_or
wm.4 0xef600b04  0xc08f            # gpio0_tcr
wm.4 0xef600b08  0x40010000        # gpio0_osrh
wm.4 0xef600b0c  0x500040aa        # gpio0_osrl
wm.4 0xef600b10  0x40010040        # gpio0_tsrh
wm.4 0xef600b14  0x0               # gpio0_tsrl
wm.4 0xef600b18  0x0               # gpio0_odr


## Setup SDRAM Controller (DDR SDRAM)
wr.4 :dcr 0x10 0x00000082 # Select SDRAM0_CLKTR
wr.4 :dcr 0x11 0x40000000 # CLKTR: Advance 90 degrees
wr.4 :dcr 0x10 0x00000080 # Select SDRAM0_TR0
wr.4 :dcr 0x11 0x410a4012 # TR0:
wr.4 :dcr 0x10 0x00000081 # Select SDRAM0_TR1
wr.4 :dcr 0x11 0x80800819 # TR1:
 
# May have to change addressing mode
wr.4 :dcr 0x10 0x00000040 # Select SDRAM0_B0CR
wr.4 :dcr 0x11 0x000a4001 # B0CR: 128M first bank, start 0x0, 13x10
wr.4 :dcr 0x10 0x00000044 # Select SDRAM0_B1CR
wr.4 :dcr 0x11 0x080a4001 # B1CR: 128M second bank, start 0x08000000, 13x10
 
wr.4 :dcr 0x10 0x00000030 # Select SDRAM0_RTR
wr.4 :dcr 0x11 0x04080000 # RTR:
wr.4 :dcr 0x10 0x00000020 # Select SDRAM0_CFG0
wr.4 :dcr 0x11 0x34000000 # CFG0: 32bit, PMU disable
wr.4 :dcr 0x11 0x84000000 # CFG0: enable SDRAM



#guardoff