# Guardian Setup for 440GX Ocotea NO SDRAM Init # # Switch Settings # U46: OFF ON OFF OFF OFF ON ON ON # 80: OFF ON ON OFF OFF ON OFF OFF # #guardon # # Target Specific # opt tar 440gx #opt tar auto #opt volt 3.3 opt volt auto opt pins form3 opt tclk norm opt tdo norm opt tdi norm opt autoexc off opt pipe off opt holddur 10000 opt clk 16 # # Auto Board Init # opt brdinit off # # General Options # opt vec low opt memread single opt memwrite single opt endian big opt step normal opt trbrk off opt excmask 0xfffff opt vchk off opt break soft opt trorg inst #opt echo off opt brkerr on opt nlines 0x0 opt nlocs 0x40 opt ascii on opt ucase off opt iradix 16 opt poly 0xedb88320 opt bloc 8bit # # flash related settings # # if you plan to use workspace for faslh programming, you can use # a large TFTP buffer and a shorter timeout value opt tsrvto 20 opt tbufsiz 32 # tftp rx buffer size -- workspace is fast, so bump to 16k # if worksace is not available or not working, use # a small TFTP buffer and a longer timeout value #opt tsrvto 30 #opt tbufsiz 4 # tftp rx buffer size -- reduce to 4k if opt flwork off # # Settings for Linux Debug # opt mmu tlb #opt mmu off #opt linver 0x02000204 #opt k_spte 0x0 #opt k_upte 0x0 #opt bloc pci # # Reset the Target # opt hreset on # try 'opt hreset rof' if flash is blank #opt reset core opt reset sys opt runn 0x400 # larger RUNN value may be needed of flash is blank reset opt runn 0x0 # Soft reset the chip # #set SDR0_SRST.DMC = 0x1 wr.4 :dcr 0xe 0x00000200 # Select EBC0_B0AP Soft Reset Register wr.4 :dcr 0xf 0x00200000 # DDR SDRAM memory controller wait 100 #set SDR0_SRST.DMC = 0x0 wr.4 :dcr 0xe 0x00000200 # Select EBC0_B0AP Soft Reset Register wr.4 :dcr 0xf 0x00000000 # DDR SDRAM memory controller # # Setup some TLBs # # Entry EPN ERPN RPN RPN_END SIZE V TS TPAR PAR1 PAR2 U0 U1 U2 U3 W I M G E UX UW UR SX SW SR PID # 0 0xF0000000 0x01 0xF0000000 0xFFFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 # FLASH at 0xF0000000 wtlb itlb 0x00 0x00 0xf0000290 0xf0000001 0x0000043f # SRAM at 0x00000000 # 1 0x00000000 0x00 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-through Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wtlb itlb 0x01 0x00 0x00000290 0x00000000 0x0000083f # Internal registers at 0x1_40000000 # 2 0xE0000000 0x01 0x40000000 0x4FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x02 0x00 0xe0000290 0x40000001 0x0000043f # Internal registers at 0x2_00000000 # 3 0xD0000000 0x02 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x03 0x00 0xd0000290 0x00000002 0x0000043f # 4 0xC0000000 0x00 0x80000000 0x80000FFF 4K Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wtlb itlb 0x04 0x00 0xc0000210 0x80000000 0x0000043f # 5 0xC0001000 0x00 0x80001000 0x80001FFF 4K Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wtlb itlb 0x05 0x00 0xc0001210 0x80001000 0x0000043f # 6 0x10000000 0x00 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wtlb itlb 0x06 0x00 0x10000290 0x00000000 0x0000043f # 7 0x80000000 0x03 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard disabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x07 0x00 0x80000290 0x00000003 0x0000043f # # clear all cache wr.4 :spr 0x370 0x00000000 #INV0 wr.4 :spr 0x371 0x00000000 #INV1 wr.4 :spr 0x372 0x00000000 #INV2 wr.4 :spr 0x373 0x00000000 #INV3 wr.4 :spr 0x390 0x00000000 #DNV0 wr.4 :spr 0x391 0x00000000 #DNV1 wr.4 :spr 0x392 0x00000000 #DNV2 wr.4 :spr 0x393 0x00000000 #DNV3 wr.4 :spr 0x398 0x0001f800 #DVLIM wr.4 :spr 0x399 0x0001f800 #IVLIM # # Flash Chip Selects # # 2 socketed Flash parts wr.4 :dcr 0x12 0x00000000 # Select EBC0_B0CR wr.4 :dcr 0x13 0xFFC58000 # 4MB at 0xFFC00000, r/w, 8bit wr.4 :dcr 0x12 0x00000010 # EBC0_B0AP wr.4 :dcr 0x13 0x04055200 # Alternate non-socketed Flash wr.4 :dcr 0x12 0x00000002 # Select EBC0_B2CR wr.4 :dcr 0x13 0xFF858000 # 4MB at 0xFF800000, r/w, 8bit wr.4 :dcr 0x12 0x00000012 # EBC0_B2AP wr.4 :dcr 0x13 0x04055200 # # Flash Setup # This is setup by agile-db # #opt flbase 0xfff80000 #opt fltype amd29f #opt flwidth 8 #opt flssize 0x10000 #opt flnsec 8 #opt flwork on #opt wsaddr 0xC0000000 #opt wssize 0x2000 #opt fltout 20 opt step noextint|thruexc # No external Interrupts while stepping opt ftimrs off # Freeze Timers when stopped? #wtlb ivt 0x1fe 0 0x10000000 9 0 # Vmap Entry for Kernel Space Applications #wtlb ivt 0x1ff 0 0xc0000000 9 0 # Vmap Entry for Kernel Space # # playback large set of register initializations quickly via the silent @play commmand # this should set things up enough to do config cycles on the PCI # Make sure the TLB mappings match the mappings for the PCI init file # or change the PCIX AND OPBA0 register addresses in the PCI init file to match your TLB mapping # for the PCIX0 group the current translation is 0x20xxxxxx to 0xDxxxxxxx # wtlb itlb 0x6 0x0 0xd0000290 0x2 0x51b # for the OPBA0 group the current translation is 0x14xxxxxx to 0xExxxxxxx # wtlb itlb 0x1 0x0 0xe0000290 0x40000001 0x51b #@play C:\etc\agile-db\agile-db\configurations\ppc_440gx_ocotea_pci.def #guardoff