# Guardian Setup for 440SPe Yucca # # # Switch Settings # SW3: OFF ON OFF OFF OFF OFF OFF OFF # # Target Specific # # ppc_440spe_yucca.def # # #guard_on # #opt tar auto opt tar 440spe opt volt 3.3 opt pins form3 opt tclk norm opt tdo norm opt tdi norm opt autoexc off opt pipe off opt holddur 20000 opt runn 0 #opt lhash on #opt lhash off # # Auto Board Init # opt brdinit off opt brdopt 0x41 # # Settings for Linux Debug # #opt mmu off opt mmu tlb # to support linux debug opt step thruexc|noextint #opt ftimrs on # Freeze Timers when stopped opt ftimrs off # off so PIBs will boot # # General Options # def - * opt vec high opt memread single #opt memwrite burst opt memwrite single opt endian big opt step thruexc|noextint #opt step normal opt trbrk off opt excmask 0xfffff opt vchk off opt break soft opt trorg inst opt echo on opt brkerr on opt nlines 0x0 opt nlocs 0x40 opt ascii on opt ucase off opt iradix 16 opt poly 0xedb88320 opt bloc 8bit #opt bloc pci # # flash related settings # # if you plan to use workspace for faslh programming, you can use # a large TFTP buffer and a shorter timeout value opt tsrvto 20 opt tbufsiz 4 # tftp rx buffer size -- workspace is fast, so bump to 8k # if worksace is not available or not working, use # a small TFTP buffer and a longer timeout value #opt tsrvto 30 #opt tbufsiz 4 # tftp rx buffer size -- reduce to 4k if opt flwork off # # # Reset the Target # opt hreset on opt reset sys opt clk 1 reset wait 200 # Soft reset the chip # ##set SDR0_SRST.GPT = 0x1 #wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register #wr.4 :dcr 0xf 0x00f00000 # DDR SDRAM memory controller #wait 100 ##set SDR0_SRST.DMC = 0x0 #wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register #wr.4 :dcr 0xf 0x00000000 # DDR SDRAM memory controller # Soft reset the chip # #set SDR0_SRST.SRAM = 0x1 wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register wr.4 :dcr 0xf 0x00002000 # SRAM memory controller wait 100 #set SDR0_SRST.SRAM = 0x0 wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register wr.4 :dcr 0xf 0x00000000 # SRAM memory controller #set SDR0_SRST.DMC = 0x1 wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register wr.4 :dcr 0xf 0x00200000 # DDR SDRAM memory controller wait 100 #set SDR0_SRST.DMC = 0x0 wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register wr.4 :dcr 0xf 0x00000000 # DDR SDRAM memory controller ##set SDR0_SRST.EBC0 = 0x1 ##wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register ##wr.4 :dcr 0xf 0x20000000 # External bus controller #wait 100 ##set SDR0_SRST.EBC0 = 0x0 ##wr.4 :dcr 0xe 0x00000200 # Select SDR0_SRST Soft Reset Register ##wr.4 :dcr 0xf 0x00000000 # External bus controller opt mmu tlb wr msr 0x00 # if you enable cache, the step from reset will not work # flash chip select wr.4 :dcr 0x12 0x0 # write IDCR config address wr.4 :dcr 0x13 0xfff18000 # ebc0_b0cr, 1Mb at 0xfff00000 ## make usre L2 is configured for use as internal SRAM wr.4 :dcr 0x30 0x00000000 # l2c0_cfg # # Group: SRAM0 for scratch or demo RAM # wr.4 :dcr 0x20 0x00000980 # sram0_sb0cr, 64Kb at 0x00000000 wr.4 :dcr 0x21 0x00010980 # sram0_sb1cr, 64Kb at 0x00010000 # TLB for cache enable during demo code #wtlb itlb 0x00 0x00 0x000002c0 0x00000308 # enable write-thru cache for RAM at 0x0 ################### TLB entries ############################### # Entry EPN ERPN RPN RPN_END SIZE V TS TPAR PAR1 PAR2 U0 U1 U2 U3 W I M G E UX UW UR SX SW SR PID ## 1Mb flash at 0xfff00000 # 00 0xFFF00000 0x01 0xFFF00000 0xFFFFFFFF 1M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wtlb itlb 0x00 0x00 0xfff00250 0xfff00001 0x0000043f ## 256Mb RAM at 0x00000000 # 01 0x00000000 0x00 0x00000000 0x0FFFFFFF 256M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-thru Cache enable No coherence Guard disabled Big Enabled Enabled Enabled Enabled Enabled Enabled 0x00000000 wtlb itlb 0x01 0x00 0x00000290 0x00000000 0x0000083f # cache enabled #wtlb itlb 0x01 0x00 0x00000290 0x00000000 0x0000053f # cache disabled ## EMAC0, GPT, IIC0 # 02 0xA0000000 0x01 0xF0000000 0xF0000FFF 4K Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard enabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x02 0x00 0xa0000210 0xf0000001 0x0000051b ## I2O0 registers # 03 0x90100000 0x01 0x00100000 0x00100FFF 4K Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard enabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x03 0x00 0x90100210 0x00100001 0x0000051b ## XOR0 registers # 04 0x90200000 0x01 0x00200000 0x00203FFF 16K Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard enabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x04 0x00 0x90200220 0x00200001 0x0000051b ## PCIX0 registers # 05 0x50100000 0x09 0x0EC00000 0x0ECFFFFF 1M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard enabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x05 0x00 0x50100250 0x0ec00009 0x0000051b ## PCIX1 registers # 06 0x51100000 0x09 0x1EC00000 0x1ECFFFFF 1M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard enabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x06 0x00 0x51100250 0x1ec00009 0x0000051b ## PCIX2 registers # 07 0x52100000 0x09 0x2EC00000 0x2ECFFFFF 1M Valid 0 0x0 0x0 0x0 Off Off Off Off Wr-back Cache inhibit No coherence Guard enabled Big Disabled Enabled Enabled Disabled Enabled Enabled 0x00000000 wtlb itlb 0x07 0x00 0x52100250 0x2ec00009 0x0000051b # speed things now that the CPU is set up opt clk 16 #guard_off