JTAG Boundary-Scan Vs. JTAG Emulation (ICE)

One question that I often hear is: “What’s difference between JTAG Boundary-Scan Test and JTAG Emulation or a JTAG ICE?”

First off, these two methods share common functions such as: hardware bring-up, device programming and even some basic hardware test functionality. The big difference is that test systems are designed to do extensive hardware testing of circuit boards and ICE tools are predominantly used to debug hardware and firmware.

While the implementation is often different, the result is the same. Let’s take a look at both methods:

JTAG Boundary Scan Test

JTAG tools are extremely powerful and are an excellent way to do device programming and board testing. In Boundary-Scan mode the JTAG chain is essentially a serial shift register that runs throughout a device.

Reading and External Device Pins

Each external pin can be set to a state or have it’s state read by manipulating the internal JTAG state machine. If you want to read a pin, figure out how many bits to stuff into the serial register, set up the state machine and clock them through. When the shifting is done, you will have the value that you need.

Writing to External Device Pins

Conversely, for setting pins, you would load the pattern up, set up the state machine and shift the bits out until they reached the pins in question.

Testing Multiple Devices on a JTAG Chain

To allow for board testing, boundary-scan enabled chips are daisy-chained together. The TMS and TRST lines are shared by every device, while the TDI and TDO lines form the daisy chain connections. The result is one long scan chain.

By reading pins and clocking out data and by writing pins via JTAG, any pin on any JTAG enabled device can be easily tested. Of course, this description is greatly simplified. In reality there are ways to put devices in so called “bypass” mode allowing them to be skipped over and ignored.

Devices can also be placed in transparent mode allowing signals to be passed through them. This Pass-through mode along with adherence to design for test (DFT) rules allows devices that are off the scan chain to be tested.

Fault Detection and API Access

Using this scheme, JTAG Boundary Scan Test tools can detect opens, shorts and “stuck at” faults on a system under test.

Using APIs and macro language interfaces, even complex device like Ethernet transceivers can be tested at an electrical and a basic functional level. Finally, programmable devices like: FLASH Memory, CPLDs, and FPGAs can be programmed in-circuit.

JTAG Emulation or JTAG ICE

A JTAG Emulator or ICE typically uses JTAG as well. (Some devices, like the Freescale Coldfire family use a BDM debug interface, while others like the Freescale MPC555 use the NEXUS interface.)

Assuming that JTAG is used–as it is on a popular device like the ARM9 core–the intent is more typically for hardware and software debug and FLASH Programming as opposed to Test.

When used as an ICE, JTAG controls and runs the microprocessor. In test mode, the processor is typically not running. An ICE also uses JTAG to communicate with the processors internal resisters allowing them to be set or read by the tool.

Special Processor Registers Support JTAG Debug

With an ICE, special registers controlled by JTAG in the processor are used to support debug functions like: Step, breakpoint, stop, run, memory and register read and write. IN order to do complex operations quickly, the JTAG channel is often used to set up the processor and it’s peripherals to work with RAM and FLASH in the system. Once the system is set up, programs can be spoon-fed to the processor’s RAM by the ICE. This is very powerful, since it all happens before the system is up and running user code.

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