JTAG  Field Programmable Gate Array (FPGA) Pin out – “Standard (CES)”

This standard configuration is typically used for FPGA (such as Xilinx) JTAG programming adapters. You can create a pinout to use our JTAG system using the description below.

Pin Number                Signal name                  Signal Description

1                                      TCK                                   Test Clock Signal

2                                    Ground                             Ground

3                                    TDI                                     Test Data In

4                                   Ground                              Ground

5                                   TDO                                     Test Data Out

6                                  VCC                                      VCC Supply

7                                  TMS                                     Test Mode Select

8                                   TRST                                   Test Reset Signal

For additional Pinout and connector information for other tools and devices, please visit our JTAG Connector Pinout Page.